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EN0-001 - ARM Accredited Engineer - Dump Information
| Vendor | : | ARM |
| Exam Code | : | EN0-001 |
| Exam Name | : | ARM Accredited Engineer |
| Questions and Answers | : | 210 Q & A |
| Updated On | : | January 4, 2018 |
| PDF Download Mirror | : | EN0-001 Brain Dump |
| Get Full Version | : | Pass4sure EN0-001 Full Version |
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EN0-001 |Latest Exams added on bigdiscountsales
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Answer: A
QUESION: 202
During
an investigation into a software performance problem an engineer
doubles the clock frequency of a cached ARM processor running the
software. Unfortunately the performance of the application does not
increase by very much, despite running on the processor for 100% of the
time. What is likely to be the main bottleneck in the system?
- The processor is context switching between multiple processes
- Performance is limited by the speed of external memory
- The processor is taking too long to execute branch instructions
- The system is raising interrupts too fast for the processor to handle them
Answer: B
QUESION: 203
Which TWO of the following options are DISADVANTAGES of building source code to use software floating point? (Choose two)
- Not all floating point arithmetic operations are supported
- Floating point calculations have lower performance than hardware floating point
- The stack cannot be used to pass floating point function arguments
- The results of floating point calculations will be less accurate
- The resulting code will be larger
Answer: B, E
QUESION: 204
A
32KB 4-way set associative instruction cache supports a cache line size
of 64 bytes. How many bits are required to index a cache line in a way?
- 6 bits
- 7 bits
- 9 bits
- 15 bits
Answer: B
QUESION: 205
In a system using the Security Extensions, how does the Secure Monitor execute a switch from Secure to Non-secure state?
- Encrypts Secure register contents, sets the NS bit in SCTLR and branches directly to Normal world code
- Saves Secure register contents, sets all registers to zero, sets the NS bit in SCTLR and branches directly to Normal world code
- Saves Secure register contents, loads Non-secure ones from memory, sets the NS bit in SCTLR and performs an exception return
- Sets the NS bit in SCTLR and performs an exception return - all registers are banked in hardware and switched automatically
Answer: C
QUESION: 206
An
ARM Cortex-A9 multi-core system has two CPUs, C1 and C2, each with a
corresponding data cache. The code running on C1 writes to a memory
location M. and C1 updates its data cache, but not main memory. After
that, C2 tries to read the contents of memory location M. Which of the
following hardware can automatically (without software inteivention)
ensure that C2 reads the updated contents of M?
- Snoop Control Unit
- Tightly Coupled Memory
- Level 2 Cache Controller
- Dynamic Memory Access Controller
Answer: A
QUESION: 207
When should an ISB instruction be used?
- When executing a long branch
- When clearing the branch predictor caches
- When reading a register from a coprocessor
Answer: B
QUESION: 208
Which of the following processors includes a Generic Interrupt Controller as a standard component?
- Cortex-A8
- Cortex-M3
- Cortex-R4F
- Cortex-A9 MPCore
Answer: D
QUESION: 209
Which of the following statements best describes a Board Support Package (BSP)?
- PC interface hardware for configuring a boot monitor
- Hardware specific source code needed for operating system support
- A working port of Linux for a specific hardware platform
- Debugging hardware and software supplied with a development board
Answer: B
QUESION: 210
What are the values of the NZCV bits in the CPSR after executing the following instructions?
LDR R0, = 0xFFFFFFFF ADDS R0, R0, #1
- 0101
- 0110
- 1001
- 1010
Answer: B
ARM EN0-001 Exam (ARM Accredited Engineer) Detailed Information
ARM Accredited Engineer ProgramThe ARM Accredited Engineer and ARM Accredited Microcontroller Engineer qualification exams are no longer available. For further information, please refer to the FAQ list below.
FAQs
Why has the program ended?
With the increasing reach of the ARM University Relations program into the education of the engineers of the future, the Partner Enablement Group took the decision to direct its resources into other areas aimed at providing knowledge-based services to professional engineers.
Can I still get a certificate (or duplicate) certificate?
For candidates who have passed an ARM Accredited Engineer exam we will issue certificates until June 30, 2016. Email certification@arm.com if you need a certificate.
Is my accreditation still valid?
Although the ARM Accredited Engineer exams are now retired, those candidates who have passed an ARM Accredited Engineer exam can still include this on their qualification history as there is no expiry date for the accreditation. The logo may still be used on personal business cards and on social media profiles e.g. LinkedIn. We have no plans to withdraw this.
Will you release any ARM Accredited Engineer exams in the future?
We do not anticipate releasing more exams in the future.
Ensure success with our high quality technical support
SoC system design and implementation is getting more complex and challenging, as cores and subsystems get more powerful yet increasingly energy efficient. ARM offers different support levels so you can reduce project risk and time to market, gain design confidence, and achieve your targets. Our team of highly qualified ARM experts are there for design advice and debug assistance via the web and email, for the duration of your support contract.
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ARM EN0-001
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